FPGA prototyping platform VCS simulation #871

jamesdunn · 2021-04-29T23:10:35Z

Related issue: #820

Type of change: new feature

Impact: software change

Release Notes

This PR contains a draft of FPGA prototyping sim support. It currently targets Arty, but I have tried to generalize the flow such that it should be able to target the VCU118 with minor changes.

The sim binary builds, but exhibits the same behavior described in #820, so please do not merge. However, I wanted to get in a PR so that the behavior can be reproduced with a make target. In that issue, the sim binary is missing the program-as-argument functionality given in testchip_tsi.cc. David suggested looking into +permissive_on/off flags, which I will do next.

To summarize what this PR contains, I have added a sim-fpga target in fpga/Makefile that runs a .tcl script, /fpga/scripts/generate_vcs_collateral.tcl, to generate Vivado behavioral sim collateral for VCS. It then runs through the VCS mixed-language flow, analyzing the Verilog and VHDL, then elaborating the simulation binary.

I will definitely do a lot of cleanup before merging this. Partcularly de-duplication between this Makefile and some things in vcs.mk that were hard-coded. Also figuring out a cleaner way to bring in an FPGA-specific testdriver, which for now uses an additional case in generators/utilities/src/main/scala/Simulator.scala for a new sim_name.

To run:

./scripts/init-fpga.sh
cd fpga
make SUB_PROJECT=artysim sim-fpga

…permanent fix since we do want this tied off for hardware.

… of adding a case in Simulator.scala for a new simulation variable, arty. This can change later.

…cies with includes in build.sbt. Will be changed later.

…mulation libraries. Next, sim-fpga target will include the VCS MX flow commands.

… rules for VCS MX flow.

… described in issue, but it can now be replicated.

…ar project dependencies.

abejgonzalez

Overall, a good start. It might be worth it to add a Makefile check for Vivado versions (what Vivado version are you using?).

fpga/Makefile

fpga/src/main/scala/arty/Configs.scala

fpga/src/main/scala/arty/TestHarness.scala

generators/utilities/src/main/resources/vsrc/ArtyTestDriver.v

…by Abe.

…check.

jamesdunn · 2021-05-05T17:29:09Z

Overall, a good start. It might be worth it to add a Makefile check for Vivado versions (what Vivado version are you using?).

Thanks for your review and comments, Abe. I have added a Makefile variable VIVADO_VERSION that gets the version. I am currently using v2019.2. I anticipate other versions being compatible, but I agree that it's good to support only one version and do a check. Do you recommend erroring out of the build on a version mismatch? If so, what make target should that be under? The bitstream generation and simulation targets are independent of one another, so I could put it under both.

fpga/src/main/scala/arty/Configs.scala

abejgonzalez · 2021-05-11T14:55:24Z

fpga/Makefile

@@ -14,6 +14,9 @@ sim_name := none
 #########################################################################################
 # include shared variables
 #########################################################################################
+
+VIVADO_VERSION := $(shell vivado -version | head -1 | grep -o -P '(?<=\s).*(?=\s)')


If Vivado isn't on the path this pollutes the terminal output. Maybe pipe stderr to /dev/null. Also, where is this checked/used?

…eset switch on the dev board.

…t module in fpga-shells depends on it, and sim config does not include JTAG module.

abejgonzalez · 2021-10-11T18:02:13Z

generators/utilities/src/main/resources/vsrc/ArtyTestDriver.v

+  end
+
+  `MODEL testHarness(
+    .CLK100MHZ(clock),


I wonder if we can avoid duplicating this file by creating a new Shell called something like ChipyardArtyShell which 1 instantiates the current ArtyShell but also renames the CLK100MHz -> clock and ck_rst -> reset (and also does the negation within it). Maybe this can also be done w/ the fancier diplomatic Arty100TShell if we don't want to hack around w/ this basic shell?

I agree that it's best to avoid keeping excess collateral files like this around. Seems like it would be a good solution to create a new shell and rename to conform to the stock CY TestDriver. I'll look at that but will want to make sure that nothing in fpga-shells depends on these names. I haven't looked as much at the diplomatic Arty100TShell but will do so. I think it would be best to make Arty diplomatic to bring it in line with the VCU118 shell.

Ideally, if the test driver is the same and the tcl scripts are generalized... then I should be able to port this work to test the VCU118. Then if that works, I can probably add both of these tests into CI.

fpga/scripts/generate_vcs_collateral.tcl

fpga/src/main/scala/arty/Configs.scala

fpga/src/main/scala/arty/HarnessBinders.scala

jamesdunn · 2021-10-11T19:34:00Z

This is now working. Users with Vivado and VCS in their paths can run

make SUB_PROJECT=artysim sim-fpga

in the fpga directory, and a sim binary should be built in generated-src/[project name]

You can then pass a program to the generated binary as with the standard RTL sim flow.

James Dunn and others added 10 commits March 15, 2021 11:45

Adding a new config for Arty simulation.

036f429

Don't tie off success IO in the harness when using sim serial. Not a …

ece1ca4

…permanent fix since we do want this tied off for hardware.

First pass at using an Arty-specific TestDriver. Done in a kludgy way…

bff86e2

… of adding a case in Simulator.scala for a new simulation variable, arty. This can change later.

Adding ArtyTestDriver in the easiest place to avoid circular dependen…

254f0c7

…cies with includes in build.sbt. Will be changed later.

Small changes to ArtyTestDriver.

193d55c

Makefile includes sim-fpga target that goes up to compiling vivado si…

bf0225f

…mulation libraries. Next, sim-fpga target will include the VCS MX flow commands.

Make rule to generate additional VCS sim collateral. Now ready to add…

1ad47a5

… rules for VCS MX flow.

More collateral generation.

975d6c0

Have Vivado generate list of System C files.

14f464a

Now have make target for building the simulation binary. Same problem…

634ab89

… described in issue, but it can now be replicated.

jamesdunn added enhancement DO NOT MERGE labels Apr 29, 2021

jamesdunn requested a review from abejgonzalez April 29, 2021 23:10

jamesdunn changed the title ~~FPGA Prototyping Platform VCS simulation~~ FPGA prototyping platform VCS simulation Apr 29, 2021

jamesdunn linked an issue Apr 29, 2021 that may be closed by this pull request

Prototyping Harness Sim Testbench #820

Closed

Removed TestDriver from old location, which didn't work due to circul…

96c45e8

…ar project dependencies.

abejgonzalez reviewed May 3, 2021

View reviewed changes

James Dunn added 3 commits May 5, 2021 10:54

Addressed spacing issues, default sim_name, and SerialTLKey comments …

badbc0a

…by Abe.

Small fix to sim_name assignment, as it is already defined.

eba846c

Adding makefile variable for vivado version, to be used in a version …

6156c7e

…check.

Less hacky project creation .tcl script.

a28e846

jerryz123 reviewed May 5, 2021

View reviewed changes

fpga/src/main/scala/arty/Configs.scala Outdated Show resolved Hide resolved

James Dunn added 2 commits May 5, 2021 16:41

Fix ordering of config fragments.

7cbc4ee

Tie off success if no TL serial

03f8fde

abejgonzalez reviewed May 11, 2021

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abejgonzalez mentioned this pull request May 12, 2021

Remove GenerateSimFiles and use make instead #879

Merged

jamesdunn mentioned this pull request May 15, 2021

Prototyping Harness Sim Testbench #820

Closed

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Fixed floating success in testharness.

6dc0d4b

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dunn added 5 commits September 21, 2021 13:41

debugging sim peripheral reset harnessbinder

54b4ebc

cleaned up binder

b2f5d89

Fixing binder ordering in config.

9a41942

Making reset active low in Arty test driver to match the active low r…

863e2d9

…eset switch on the dev board.

Setting SRST_n (JTAG reset, active low) to true by default. Arty rese…

9b0f10f

…t module in fpga-shells depends on it, and sim config does not include JTAG module.

abejgonzalez reviewed Oct 11, 2021

View reviewed changes

Making VCS run in debug mode in sim-fpga make target.

dff7d2c

jamesdunn removed the DO NOT MERGE label Oct 13, 2021

jamesdunn changed the base branch from master to dev October 13, 2021 20:42

James Dunn and others added 5 commits October 14, 2021 15:58

Merging dev into arty-sim to synchronize.

e45f82d

Cleanup.

2bcc78a

Comments.

8f48540

Parameterizing testbench in sim flow

c2d00ae

Merge branch 'dev' into arty-sim

7c55be1

sagark added this to the unknown-future milestone Jun 15, 2022

abejgonzalez closed this Feb 15, 2023

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FPGA prototyping platform VCS simulation #871

FPGA prototyping platform VCS simulation #871

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FPGA prototyping platform VCS simulation #871

FPGA prototyping platform VCS simulation #871

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